Product Description:
National Instruments Corporation 780342-01 PXI-7854R R Series Multifunction, Virtex-5 LX110, 8 AI, 8 AO, 96 DIO, 750kS/sec
- 8 analog inputs, independent sampling rates up to 750 kHz, 16-bit resolution, 10 V
- 8 analog outputs, independent update rates up to 1 MHz, 16-bit resolution, 10 V
- 96 digital lines configurable as inputs, outputs, counters, or custom logic at rates up to 40 MHz
- Virtex-5 LX110 FPGA programmable with the LabVIEW FPGA Module
- 3 DMA channels for high-speed data streaming
- Configure Complete PXI System
- View Data Sheet
View Support Resources
The NI PXI-7853R multifunction reconfigurable I/O (RIO) module features a user-programmable FPGA chip for onboard processing and flexible I/O operation. You configure all analog and digital functionality using NI LabVIEW graphical block diagrams and the LabVIEW FPGA Module. Your block diagram executes in the hardware, giving you direct, immediate control over all I/O signals to deliver high-performance capabilities such as the following:
-Complete control over the synchronization and timing of all signals and operations
-Custom onboard decision making that executes with hardware-timed speed and reliability
-Digital lines individually configurable as inputs, outputs, counter/timers, PWM, flexible encoder inputs, or specialized communication protocols
NI R Series multifunction RIO devices feature a dedicated analog-to-digital converter (ADC) per channel for independent timing and triggering. This offers specialized functionality such as multirate sampling and individual channel triggering, which are outside the capabilities of typical DAQ hardware. Common examples include custom discrete and analog control, sensor simulation, rapid prototyping, hardware-in-the-loop (HIL) test, digital protocol emulation, and other applications that require precise timing and control.
Required Software
This product requires the NI LabVIEW FPGA Module Version 8.6 or later and NI-RIO Version 3.0 or later driver software.
Virtex-5 FPGA
The Virtex-5 FPGA architecture is optimized to execute faster and more efficiently using single-cycle Timed Loops in LabVIEW FPGA. This means you can optimize more LabVIEW FPGA code to fit within Virtex-5 FPGAs and execute more operations per clock cycle.
Recommended Accessories
The NI SHC68-68-RMIO cable is designed and shielded specifically for the multifunction I/O connector (connector 0) of R Series devices. The NI SHC68-68-RDIO cable is designed and shielded specifically for the digital I/O connectors (connectors 1 and 2) on R Series devices to reduce crosstalk for improved signal integrity and noise rejection.
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