The Agilent E9520A Inverse Assembler for the Motorola MPC8540 and MPC8560 simplifies debug by disassembling instruction fetches into PowerQUICC III mnemonics. Support is provided for both the Local Bus General Purpose Chip Select Machine (GPCM) and for the DDR Bus. Connection to the analyzer may be made using Mictor connectors, Samtec connectors or soft touch connectorless probing provided by the user according to Agilents design guide recommendations. Support for PCI is available separately from Agilent.
Logic analyzer configuration options:
Application Support for Agilent Logic Analyzers
Motorola PowerQUICC Logic Analyzer User's Guide
GPCM Interface
- Signals disassembled into PowerQUICC III mnemonics for instructions
- Support for cache-on trace mode
- Optional disassembly with simplified mnemonics
- Optional source code correlation
DDR Interface
- Signals disassembled into PowerQUICC III mnemonics for instructions
- Supports full 333 M Transfers/sec
- Captures both read and write data on their respective clock phases
- Decodes DDR cycle type (Deselect, Active, Read, Write, Mode Register, etc.)
- Decodes data cycle type (Instruction read, Data Read, Data Write)
- Decodes Addresses: RAS/CAS addresses decoded into linear physical addresses
- Support for cache-on trace mode
- Optional disassembly with simplified mnemonics
- Optional source code correlation